1. Field of the Invention
The present invention relates to, e.g. a Bi-CMOS LSI, and more particularly to a semiconductor device including bipolar transistor having an emitter electrode formed by using a polysilicon, and a process of manufacturing the semiconductor device.
2. Description of the Related Art
A semiconductor device including a bipolar transistor, e.g. a Bi-CMOS LSI, employs a bipolar transistor having such a structure that an emitter electrode is formed by using a polysilicon in order to reduce power consumption and enhance integration density and performance. This type of bipolar transistor is disclosed in, e.g., IEEE TRANSACTION ON ELECTRON DEVICES, VOL. ED-34, NO. 6, JUNE 1987 "High-speed Bi-CMOS Technology with a Buried Twin Well Structure" TAKAHIDE IKEDA et al., p. 1304.
In the bipolar transistor, a polysilicon layer containing impurities is formed on part of an inner base region. The polysilicon layer is used as a diffusion source, and impurities are introduced into the inner base region, thereby forming an emitter region. According to this manufacturing process, there can be obtained an emitter region having a less diffusion depth and a smaller size than an emitter region formed by ion implantation. Thus, the depth of the base region can also be reduced. Thereby, a base current and a base resistance can be decreased. Accordingly, the switching speed of the bipolar transistor can be increased and the size thereof can be reduced.
The polysilicon used as the emitter electrode has, in general, a high sheet resistance of, e.g. 200.OMEGA./ . It is desirable, therefore, that a contact portion between an emitter electrode and an aluminum interconnection wire formed on the emitter electrode be located as close as possible to a contact portion between the emitter electrode and an emitter region. The greater the distance therebetween, the higher the emitter resistance. It is most desirable that the two contact portions vertically overlap each other.
In this case, however, it is necessary to arrange the aluminum wire connected to the emitter electrode in the vicinity of the aluminum wire connected to the base region, with a predetermined distance provided therebetween. Thus, the location at which to form the contact portion between the emitter electrode and the associated aluminum wire is limited. As a result, the two contact portions cannot necessarily be located to overlap each other. For the overlapping arrangement of the contact portions, the area of the outer base region must be increased. If the outer base region is enlarged, there occurs a problem that the base capacity of the bipolar transistor increases.
In the technical field of Bi-CMOS LSIs, with the miniaturization of MOS transistors which constitute a CMOS circuit, an electrically conductive material is buried in contact holes for connecting aluminum wiring and active regions such as a source and a drain formed in the semiconductor substrate, in order to improve step coverage. In order to obtain the same step coverage of the bipolar transistor region as the step coverage of the MOS transistor region, it is also desirable to bury an electrically conductive material between the aluminum wiring and the polysilicon layer serving as emitter electrode.
However, if the two contact portions are arranged to overlap each other and the electrically conductive material is deposited on the emitter electrode (polysilicon layer) in the contact hole by means of, e.g. a CVD process, the conductive material grows abnormally at the stepped portion of the polysilicon layer, with the result that a void forms in the vicinity of the stepped portion. Thus, the emitter resistance increases and the electrical characteristics of the bipolar transistor considerably deteriorate.